期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

亚100纳米级标准单元的可制造性设计 被引量：3

Design for Manufacturability of Sub-100 Nanometer Standard Cells
下载PDF
导出
摘要 本文介绍了亚 10 0纳米工艺可制造性验证的一组工艺仿真和错误定位技术 ,制定了标准单元可制造性设计 (DFM ,DesignForManufacturability)的流程 ,重点讨论了在亚 10 0纳米工艺条件下标准单元设计中遇到的一些典型可制造性问题 ,提出了相应的新设计规则和解决方案 .依靠以上DFM技术方法 ,完成了实际 90nm工艺标准单元可制造性设计工作 . A group of technologies for sub-100 nm process modeling and DFM (Design For Manufacturability) problem are presented. A DFM flow for standard cell design is implemented, with typical DFM patterns being discussed in detail. New design rules and solution styles are introduced as well. Based on the DFM flow and design styles, a set of DFM-friendly 90 nm standard cells are designed.
作者 张培勇 严晓浪 史峥 高根生 马玥 陈晔
机构地区 浙江大学超大规模集成电路设计研究所
出处 《电子学报》 EI CAS CSCD 北大核心 2005年第2期304-307,共4页 Acta Electronica Sinica
基金 国家自然科学基金 (No .60 1 760 1 5 No .90 2 0 70 0 2 ) 863高技术计划 (No .2 0 0 2AA1Z1 4 60 No.2 0 0 3AA1Z1 370 )
关键词 标准单元 可制造性设计 分辨率增强技术 Integrated circuit layout MOS devices Photolithography Printed circuit design Quality control Silicon
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献9

  • 1Lefebvre M,et al.The future of custom cell generation in physical synthesis[A].Design Automation Conference[C].Anaheim,California,United States,1997.446-451.
  • 2Kahng A B,et al.Subwavelength lithography and its potential impact on design and EDA[A].Design Automation Conference[C].New Orleans,Louisiana,United States,1999.799-804.
  • 3Wong A K.Microlithography:trends,challenges,solutions,and their impact on design[J].Micro,IEEE,2003,23(2):12-21.
  • 4高根生,史峥,陈晔,严晓浪.一种用于标准单元版图交替移相掩模相位兼容性规则检查的工具[J].Journal of Semiconductors,2004,25(5):601-606. 被引量：3
  • 5Torres J A,et al.RET compliant cell generation for sub-130nm processes[A].Proc.Design,Process Integration,and Characterization for Microelectronics[C].Santa Clara,California,United States,2002,SPIE Vol.4692,529-539.
  • 6陈志锦,史峥,王国雄,付萍,严晓浪.一种快速光刻模拟中二维成像轮廓提取的新方法[J].Journal of Semiconductors,2002,23(7):766-771. 被引量：12
  • 7Xiaolang Y,et al.Architecture of a post-OPC silicon verification tool[A].ASICON[C].Beijing,2003.1365-1368.
  • 8Hindmarsh R D.JOGM:A CMOS cell layout style using jogged transistor gates[A].Design Automation Conference[C].Grenoble,France,1993.48-53.
  • 9Terasawa T.Embedded tutorial:subwavelength lithography[A].Proceedings of the ASP-DAC 2000[C].Yokohama,Japan,2000.295-300.

二级参考文献8

  • 1Chen Zhijin,Shi Zheng,Wang Guoxiong,et al.A new me-thod of 2D contour extraction for fast simulation of photolithographic process.Chinese Journal of Semicondcutors,2002,23(7):766(in Chinese)[陈志锦,史峥,王国雄,等.一种快
  • 2Levenson M D,Viswanathan N S,Simpson R A.Improvingresolution in photolithography with a phase-shifting mask.IEEE Trans Electron Devices,1982,29:1828
  • 3Kahng A B,Wang H,Zelikovsky A.Automated layout andphase assignment techniques for dark field alternating PSM.SPIE 11th Annual BACUS Symposium on Photomask Technology.SPIE,1998,1604:222
  • 4Sanie M,Hurat P.Automated practical application of full feature alternating phase-shifting technology for a phase-ware standard-cell design flow.Design Automation Conference,2001:93
  • 5Kahng A B,Vaya S.Shifter new graph biparti-zations fordouble exposure,bright field alternatingphase-shifting mask layout.Design Automation Conference,2001:133
  • 6.[EB/OL].http:∥www.synopsys.com/products/ntimrg/pdfs/FullPhase.pdf,.
  • 7.[EB/OL].http:∥www.synopsys.com/products/ntimrg/pdfs/CostEffectiveApp.pdf,.
  • 8石瑞英,郭永康.光学邻近校正改善亚微米光刻图形质量[J].半导体技术,2001,26(3):20-26. 被引量：5

共引文献11

同被引文献19

  • 1郭琦,李惠军.超大规模集成电路的可制造性设计[J].微纳电子技术,2005,42(9):435-439. 被引量：1
  • 2李季,史峥,沈珊瑚,陈晔.亚波长光刻离轴照明和次分辨率辅助图形技术[J].江南大学学报（自然科学版）,2006,5(6):679-684. 被引量：2
  • 3赵珉,杨清华,刘明,陈宝钦.可制造性设计在纳米SOC中的应用和发展[J].微纳电子技术,2007,44(6):282-288. 被引量：2
  • 4Chang Runzi, Cao Yu, Costas J Spanos. Modeling the Electrical Effects of Metal Dishing Due to CMP for On - Chip Interconnect Optimization[J]. IEEE Trans. on Electron Devices,2004,51(10):1 577 - 1 583.
  • 5Calhoun B H, Cao Yu, Li Xin, et al. Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS [J]. Proceedings of IEEE,2008,96(2) :343 - 365.
  • 6Puneet Gupta, Andrew B Kahng, Chul - Hong Park, et al. Wafer Topography - Aware Optical Proximity Correction [J]. IEEE Trans. on Computer - Aided Design of Integra - ted Circuits and Systems,2006,25(12) :2 747 - 2 755.
  • 7Enderling S, Brown C L, Smith S,et al. Sheet Resistance Measurement of Non - standard Cleanroom Materials Using Suspended Greek Cross Test Structures [J]. IEEE Trans. on Semiconductor Manufacturing, 2006,19 ( 1 ) : 2 - 9.
  • 8Smith S,Walton A J, Ross A W S,et al. Evaluation of the Issues Involved with Test Structures for the Measurement of Sheet Resistance and Linewidth of Copper Damascene Interconnect[A]. Proceedings of 2001 International Conference on Microelectronic Test Structures[C]. Kobe,Japan, 2001:195 - 200.
  • 9Linda M Hoad, Harry A Schafft. An Evaluation of Electrical Linewidth Determination Using Cross - Bridge and Multi - Bridge Test Structures[A]. 1999 IEEE International Integrated Reliability Workshop Final Report[C] Lake Tahoe, 1999 : 41 -45.
  • 10Kelvin Yih- Yuh Doong,Jurcy Cho- His Huang, Chia- Chi Chu,et al. Infrastructure Development and Integration of Electrical - Based Dimensional Process Window Che- cking[J]. IEEE Trans. on Semiconductor Manufacturing, 2004,17(2):123 - 141.

引证文献3

二级引证文献1

电子学报
2005年 第2期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部