n^＋p^＋p—n结隔离CMOS铝栅工艺

A CMOS Al-Gate Process With n￣+p￣+p-n Junction Isolation

本文介绍一种新的ｎ￣＋ｐ￣＋ｐ－ｎ结隔离铝栅大规模集成电路工艺。它与常规铝栅ＣＭＯＳ工艺的重要区别在于，采用ｎ￣＋ｐ￣＋ｐ－ｎ结隔离技术，芯片上无低掺杂浓度区与厚的场氧化绝缘膜，场氧化膜与栅氧化膜在同一工序中完成并且厚度相接近。文中重点阐述了ｎ￣＋ｐ￣＋ｐ－ｎ结隔离击穿与ｎ￣＋，ｐ￣＋区掺杂浓度ｐ－ｎ结深度和器件特征尺寸之间的关系以及该工艺在电路中的应用等问题。

novel VLSI process using n￣+p￣+p-n junction isolated Al-gate is presented in the papor.The new processdiffers from the conventional Al-gate CMOS process in that there are no low doping concentration regions and thick fieldoxide films on the chip due to n￣+p￣+p-n junction isolation and that the field oxide and gate oxide are grown in one step. so thicknesses of the two films are very clase. The dependence ofn￣+p￣+p-n junction breakdown on the doping concentra-tions in n￣+/p￣+regions p-n junction depth and the device's feature size is descried. Application of the process to circuitsis also dealt with .