JPEG2000高速MQ编解码器的VLSI实现

A VLSI Implementation of a High-Speed MQ-Codec for JPEG 2000

提出了一种应用于JPEG2000标准的高速MQ编解码器的VLSI架构.该架构对JPEG2000中的标准MQ编解码流程进行了优化,采用条件判断归纳化简、零检测和整体移位等方法来达到高速编解码的目的.采用3级流水线结构的MQ编解码器架构,编解码器的工作效率可以达到1bit/cycle,并且在速度与面积之间达到了很好的平衡.

A high-speed MQ-codec VLSI architecture for JPEG 2000 standard is presented. The architecture optimizes the standard JPEG 2000 MQ encoding and decoding flow, accelerating the encoding and decoding with simplified conditional judgment, zero detection and whole shifting. The MQ-codec presented adopts a 3-stage pipeline architecture. Its speed is up to 1 bit/cycle. A good trade-off between speed and area is achieved.