IIC总线控制器IP核设计

Design of an IIC Bus Controller IP Core

本文详述了一种基于AMBA总线接口的IIC总线控制器IP核设计 ,给出了该IP核的系统结构以及各个子模块的详细设计方法 ,并对该IP核进行了功能仿真、FPGA原型验证 ,可测性设计以及综合。最后给出了采用Fujitsu提供的CE6 6工艺库的综合结果以及性能参数。

This paper presents design of an IIC bus controller IP core with a AMBA interface. It describes system architecture and detail design method of every sub-module and gives methods about function simulation, FPGA prototype verification, design for test and synthesis of this IP core. At last, it gives performance of the IP core synthesized under the Fujitsu's CE66 library.