Analysis and Implementation of Traffic Buffering in EOS Chip Design

Analysis and Implementation of Traffic Buffering in EOS Chip Design

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摘要 The traffic buffering problems in the ethernet over synchronous digital hierarchy(EOS) are introduced and analyzed. Different solutions are also presented in detail. Synchronous DRAM(SDRAM) is used as off-chip buffer to store-and-retransmission ethernet frames. A new and easy control design is introduced here. The buffer area size on chip is greatly reduced and the power dissipation is lowed at the same time. The traffic buffering problems in the ethernet over synchronous digital hierarchy(EOS) are introduced and analyzed. Different solutions are also presented in detail. Synchronous DRAM(SDRAM) is used as off-chip buffer to store-and-retransmission ethernet frames. A new and easy control design is introduced here. The buffer area size on chip is greatly reduced and the power dissipation is lowed at the same time.

作者 FENGBo LIUHao YINYan-fen

机构地区 WuhanResearchInstituteofPostsandTelecommunications

出处《Semiconductor Photonics and Technology》 CAS 2005年第1期12-15,共4页 半导体光子学与技术（英文版）

关键词 BUFFERING BANK ETHERNET SDRAM SDH EOS TIMING EOS 芯片设计 SDRAM SDH 通信隔离

分类号 TN929.11 [电子电信—通信与信息系统]

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1ITU-T Rec. G. 7041. Generic Framing Procedure (GFP)[Z]. Dec. 2003.
2Ramamurti V, Siwko J, Young G, et al. Initial implementations of point-to-point ethernet over SONET/SDH transport[J]. IEEE Communication Magazine, 2004, 42(3) : 64-72.
3IEEE 802. 3. IEEE Standard for Information Technology Telecommunications and Information Exchange Between Systems - Local and Metropolitan Area Networks - Specific Requirements - Part 3.. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications[S]. 2002.
4JEDEC standard[S]. 2000, No. 21-C, 3.11.

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Semiconductor Photonics and Technology

2005年第1期

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Analysis and Implementation of Traffic Buffering in EOS Chip Design

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