摘要
文章设计并实现了基于FPGA的双线性插值放大,设计中针对硬件实现,对算法的并行计算结构进行了优化。实验表明应用该方法插值计算结构简单,计算误差小,精度与软件实现相当,可实现变倍率的实时视频图像放大。
In this paper,the design and realization of bilinear interpolation enlargement based on FPGA are proposed.The structure of the algorithm is parallelized and optimized according to the characteristics of realization of hardware circuit.Experiments are also presented to prove that the method has simplified structure,low computational error,similar precision as that of software realization,and can realize variable folds of enlargement of video rate image in real-time.
出处
《计算机工程与应用》
CSCD
北大核心
2005年第8期108-110,130,共4页
Computer Engineering and Applications
基金
国家自然科学基金重点项目(编号:60135020)
国家部委基金资助
关键词
FPGA
双线性插值
图像放大
FPGA,bilinear interpolation,image enlargement