摘要
一般电路的暂态输出时间相对不是很长 ,而且电路的输入触发信号时间应小于输出时间的长度 ,这种电路设计思想有时满足不了某些场合的实际工程需要。为此 ,本文结合工程实际需要给出了利用FPGA设计超周期延时功能模块 ,该模块能准确的进行时序控制 ,可以不修改硬件满足时序要求。
In the applications of technology, using traditional method, the delay time is limited by the old idea. We select the FPGA to design delay time and develop the system of timing control. This paper introduces their design idea, the practice demonstrate that our project can exactly carry out delay timing control. With this objective when the sequential control needs to be changed, we also can realize new sequential control and don't modify the hardware.
出处
《宇航计测技术》
CSCD
2005年第1期43-45,共3页
Journal of Astronautic Metrology and Measurement