Cache中TLB的设计及优化

Design and optimize of the TLB in Cache

当今微处理器的设计中,为了加快虚拟地址向物理地址转换的速度,通常使用地址转换后备缓冲器TLB(translationlookasidebuffer)来加快地址转化的速度.本论文基于逆向设计,提出了一种可行的TLB结构,可完成地址转换的功能,并从硬件上支持了不同大小的页表格式.此外,通过引入DVS技术将TLB存储单元中的漏电功耗减少90%以上.

In nowadays' microprocessor design, the TLB is widely used to speed up the translation speed from virtual address to physical address. Based on the adverse design, an applicable TLB structure supporting the different page sizes besides the address translation is proposed. In addition, a DVS technology is used reducing the leakage power in the TLB's memory cells by 90%.