一种高速Viterbi译码器的优化设计及Verilog实现

Verilog Implementation and Optimized Design of a High Speed Viterbi Decoder

文章设计了一种高速Viterbi译码器该设计基于卷积码编码及其,Viterbi译码原理,完成了Viterbi译码的核心单元算法的优化,并采用Verilog语言编程实现了卷积码编码器和译码器。仿真和综合的结果表明本文设计的译码器速率达50Mbit/s,同时译码器的电路规模也通过算法得到了优化。

A high speed Viterbi Decoder is designed in this paper. Based on principles of convolution coding and Viterbi decoding , the algorithm of key units of Viterbi decoding is optimized and completed in this paper. Convolution coder and Viterbi decoder are implemented in Verilog HDL. The results of simulation and synthesis show that the decoding rate of Viterbi decoder is up to 50 M bit per second and the scale of decoder circuilt is also optimized by improved algorithm.