SMDSP浮点数字信号处理器CPU内功能单元的设计

The Design of Function Units in CPU for SMDSP Floating-Point Digital Signal Processor

下载PDF

导出

摘要 SMDSP是针对专门应用开发的高性能32位浮点数字信号处理器,其CPU内有独立的ALU、乘法器、数据地址产生器和六条局部数据总线,实现了乘加运算并行,算术运算与地址运算并行,加快了数据处理速度。数据地址产生器支持顺序、倒位序、循环三类数据地址的计算,使得SMDSP能方便高效地应用于数字信号处理系统。 SMDSP is a high performance 32-bit floating-point Digital Signal Processor developed for special application. SMDSP CPU consists of ALU?Multiplier?Address Generator and six local data buses, which can carry out not only Addition and Multiplication but also Arithmetic and Address operation in parallel, so it accelerates processing speed obviously. SMDSP can be used in DSP system conveniently and efficiently by the design of Sequential ? Bit-Reversed and Circular addressing mode. SMDSP is fabricated in a 0.5um three-mental CMOS process, the area is 6.2×6.7mm2, and the operation frequency is 50MHz.

作者车德亮刘文平

机构地区西安微电子技术研究所

出处《微电子学与计算机》 CSCD 北大核心 2005年第2期183-187,共5页 Microelectronics & Computer

关键词浮点数字信号处理器 CPU 加法器乘法器数据地址生成器 Floating-point digital signal processor (FDSP), CPU, Adder, Multiplier, Address generator

分类号 TP332 [自动化与计算机技术—计算机系统结构]

引文网络
相关文献

参考文献16

1蒋安平.[D].西安微电子技术研究所,1997.
2R M Jessani, M Putrino. Comparison of Single and Dual-Pass Multiply-Add Fused Floating-Point Units. IEEE Trans. Computers, 1998,47(9): 927-937.
3S Briggs, D W Matula. A 17x69 Bit Multiply and Add Unit with Redundant Binary Feedback and Single Cycle Latency. IEEE Symp.Computer Arithmetic, 1993: 163-170.
4E Hokenek, R K Montoye. Leading-zero Anticipator in the IBM RISC System/6000 Floating-Point Execution Unit.IBM Journal of Research and Development, January 1990.
5Texas Instruments. TMS320C3XUser'sGuide, 1997.
6许琪.[D].西安微电子技术研究所,2002.
7L iem C, Paulin P, et al. Address Calculation for Retargetable Compilation and Explorat ion of Instruction Set Architectures. In: Proceedings of the 33rd ACM Design Automat ion Conference, 1996: 597-600.
8L eupers R, M arwedel P. A lgo rlthm s for address assignment in DSP code generation. In: Proceedings of the IEEE International Conference Computer -Aided Design,1996:109-112.
9Sudarsanam A, L iao S, Devadas S. Analysis and evaluation of address arithmetic capabilities in custom DSP architecture. In: Proceedings of the 34th ACM Design Automat ion Conference, 1997: 287-292.
10奥本海姆谢弗.数字信号处理[Z].,..

1车德亮,许琪,沈绪榜.可编程浮点数字信号处理器LS-DSP数据路径的设计[J].信号处理,2006,22(1):86-90.
2ADI推出SHARCDSP产品组合[J].单片机与嵌入式系统应用,2010(5):86-86.
3SHARC 2148x/47x:32位浮点DSP[J].世界电子元器件,2010(9):26-26.
4蒋学程,郑忠楷.基于nRF905实现TMS320C6711无线通信[J].闽江学院学报,2006,27(5):81-83.
5赵建芬.ADSP—21061软件开发[J].电子计算机,2001(1):47-51.
6世健.AD公司高水平浮点数字信号处理器[J].世界电子元器件,1997(3):16-17.
7德州仪器成功突破低功耗挑的DSP与应用处理器[J].通信世界,2008(29).
8张雄伟.TMS320C31系列讲座(1)——第一讲高性能浮点数字信号处理器TMS320C31[J].军事通信技术,1996,0(2):75-80.
9高性能、低功耗32位浮点数字信号处理器[J].今日电子,2010(5):66-66.
10ADI最新SHARC处理器片上内存扩大250%且功耗降低20%[J].中国集成电路,2011,20(10):55-55.

微电子学与计算机

2005年第2期

浏览历史

内容加载中请稍等...

SMDSP浮点数字信号处理器CPU内功能单元的设计

参考文献16

相关作者

相关机构

相关主题

浏览历史