现场可编程门阵列中数据接口的同步设计

A Synchronous Design of Digital Interface in FPGA

在现场可编程门阵列(FPGA)的设计中,完全同步的设计应该自始至终由同一个时钟的同一个时钟沿来驱动所有的触发器。同步设计应当遵循这两个原则,以保证系统的完全同步,避免由异步产生的毛刺和时钟延迟等与时序相关的问题。列举了主机与硬盘之间的数据接口的设计,探讨同步设计的原则与方法。

In FPGA design, a synchronous design can avoid many potential timing problems such as glitches, clock skew, setup/hold time violation and racing, which should be defined according to whether or not all flip-flops /latches are driven by the same clock edge of the same clock net in the system. Through the design of a digital interface between host and ATA hard disk, some techniques and principles are groped.