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使用重复播种和Golomb编码的二维测试数据压缩 被引量:2

Two-Dimensional Test Data Compression Using Reseeding and Golomb Codes
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摘要 提出了一种用于SOC测试的二维测试数据压缩方案 先利用线性反馈移位寄存器重复播种技术 ,对带有无关位的测试向量进行压缩 ,并获得种子差分序列 ;然后用Golomb编码的方法对其作进一步的压缩 ;同时给出了Golomb码参数m的确定方法和相应的二维解压结构 实验结果表明 ,该方案在保证较高故障覆盖率的前提下 ,既能显著地减少测试序列长度、缩短测试时间 。 A two-dimensional test data compression scheme for System-On-a-Chip (SOC) is proposed. By utilizing the technique of LFSR reseeding, the test patterns with unspecified bits are first compressed, and then the seed difference sequences obtained are further compressed with Golomb codes. In the meantime, determination of the Golomb code parameter m and the corresponding two-dimensional decompression architecture is also given. Experimental results show that the scheme, under the precondition of ensuring higher fault coverage,not only reduces the length of test sequences and shortens test time, but also lowers effectively the requirement for test data bandwidth.
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2005年第3期394-399,共6页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金 (90 40 70 0 7 60 3 72 0 0 1)
关键词 SOC测试 二维压缩 重复播种 Golomb编码 解压结构 system-on-a-chip(SOC) test two-dimensional compression reseeding Golomb codes decompression architecture
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参考文献9

  • 1Zorian Yervant, Marinissen ErikJan, Dey Sujit. Testing embeddedcore based system chips[A]. In: Proceedings ofInternational Test Conference, Washington DC, 1998. 130~143
  • 2Abhijit Jas, Nur A. Touba. Test vector decompression via cyclical scan chains andits application to testing corebased designs[A]. In: Proceedings of International TestConference, Washington DC, 1998. 458~464
  • 3Anshuman Chandra, Krishnendu Chakrabarty. Test data compression for systemonachipusing Golomb codes [A]. In: Proceedings of 18th IEEEVLSI Test Symposium, Montreal, 2000.113~120
  • 4Anshuman Chandra, Krishnendu Chakrabarty. Frequencydirected runlength (FDR) codeswith application to systemonachip test data compression[A]. In: Proceedings of 19th IEEEVLSI Test Symposium, Marina Del Rey, California, 2001. 42~47
  • 5Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, et al. Builtin test forcircuits with scan based on reseeding of multiplepolynomial linear feedback shiftregisters[J]. IEEE Transactions on Computers, 1995, 44(2): 223~233
  • 6Savir J, McAnney William H. A multiple seed linear feedback shift register[J]. IEEETransactions on Computers, 1992, 41(2): 250~252
  • 7谢永乐,陈光■.数字电路多加权集随机测试生成方法[J].计算机辅助设计与图形学学报,2002,14(6):571-573. 被引量:2
  • 8Hamzaoglu Ilker, Patel Janak H. Test set compaction algorithms for combinationalcircuits[J]. IEEE Transactions on ComputerAided of Integrated Circuits and Systems, 2000,19(8): 957~963
  • 9Brglez Franc, Fujiwara H. A neutral netlist of 10 combinational benchmark circuitsand a special translator in FORTRAN[A]. In: Proceedings of International Symposium onCircuits and Systems, Kyoto, 1985. 151~158

二级参考文献3

  • 1[1]Amitava Majumder.On evaluating and optimizing weights for weighted random pattern testing[J].IEEE Transactions on Computers, 1996, 45(8):904~916
  • 2[2]Irith Pomeranz, Subhakar M Reddy.3-weighted pseudo-random test generation based on a deterministic test set for combinational and sequential circuits[J].IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 1993, 12(7):1050~1058
  • 3[3]Rohit Kapur, Srinivas Patil, Thomas J Snethen, et al.A weighted random pattern test generation system[J].IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 1996, 15(8):1020~1025

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