一种特殊激励的Verilog实现

An Implementation of a Special Stimulus in Verilog

验证是集成电路设计中的一个重要环节,而验证的主要过程可以分为向待验证模块(DUV)输入激励和观察输出结果两个步骤。不同的输入激励对应着不同的波形,其实现方式也可能不同。本文介绍了一种特殊激励的实现形式,提出了使用函数对线性激励随机产生器进行修改的方法,可以自由控制激励的高电平TH和低电平TL的百分比。

Verification is a very important step in integrated circuit design.The process of verification is divided into two steps:inputting stimulus to design under verification and observing the output results.Different inputting stimulus has different waves and has different implementation forms. An implementation of a special stimulus is introduced, which use a function into a random serial stimulus generator and result in high level and low level controlling, and which is implementation in Verilog in the end.