基于FPGA的误码率测试仪的设计与实现

Design and realization of bit error ratio tester based on FPGA

本文提出了一种使用FPGA实现误码率测试的设计及实现方法。该设计可通过FPGA内建的异步串行接口向主控计算机传递误码信息,也可以通过数码管实时显示一段时间内的误码率。文章先介绍了系统构成和工作流程,然后重点分析了关键技术的实现。

This paper presents a design for bit error ratio test using FPGA. This design can either transfer bit error information to control computer through the UART interface built inside the FPGA, or display the bit error rate by 7-segment LED. The paper first introduces the architecture and working flow of the design, and then gives the method of realization of some key techniques.