CMOS集成电路中Glitch Power的分析方法研究

A Study on Methodology for Glitch Power Analysis in CMOS IC's

在集成电路中器件延迟数学模型的基础上,介绍了如何利用定时布尔函数和定时有序二值决策图对集成电路GlitchPower进行分析;借助CUDD软件包,构建了电路的Timed-OBDD表达形式,对一些典型的BenchMark进行了仿真。

Based on the unit delay model, the analysis of glitch power in CMOS integrated circuits using timed Boolean function and timed reduced ordered binary decision diagram is presented. With the help of CUDD package, the timed-OBDD representation is built, and typical benchmarks are simulated.