FPGA实现的基4FFT处理器高效排序算法研究

Efficient Sorting Architecture for Radix-4 FFT in FPGA

在FFT处理器的设计中,蝶形处理部件是关系整个处理器运行速度与资源的核心部分。对于1 0 2 4点的FFT复数浮点运算,本文旨在提出一种高效的基4排序算法,该算法基于按时间抽取的基4FFT,结合了流水线和并行方式的特点,利用4个循环序列进行时序控制,用3个实数乘法器实现基4蝶形的3次复数乘法,相对于传统的基4FFT算法可以节省75 %的乘法器逻辑资源。实验结果表明,用该算法设计的1 0 2 4点复数基4FFT处理器在1 0 0 MHz的主时钟频率下运算速度为5 1 .2 9μs,满足了FFT运算的高速实时性要求。由于该排序思想可以较方便地扩展到基8或基1 6,但不增加进行一次基本蝶算的时钟周期数,依然是4个,故对于高基数将具有更高的效率。

The novel sorting architecture of the FFT processor is presented based on radix-4 decimation-in-time algorithm. By combining both the pipeline and parallel schemes, the proposed radix-4 butterfly uses three real multipliers and nine real adders, which leads to reduce multipliers of conventional 75%. The processor based on FPGA can operate at 100 MHz and calculate the 1 024 floating-point complex FFT in 51 29 μs. So it satisfies the needs of both small area and high speed. Furthermore, since the sorting architecture can be easily upgraded for radix-8, radix-16FFT algorithm, and donot increase the clocks required for computing a radix-r butterfly, it will be more efficient for the high radix.