新的面积有效的整数平方根电路设计

Area-efficient integer square root algorithm

针对参数化的整数平方根电路设计方法在位宽较小时存在的问题,提出了位宽为8的面积有效的整数平方根电路设计方法.首先,通过对一些平方数据的分析,找出了按照四舍五入原则计算其整数平方根的取值范围;然后,根据取值范围的不同,把平方根计算以全部选择电路实现,仿真结果表明,相对于参数化的快速收敛平方根算法有Modelsim 5 .6提供的平方根算法,提出的方法频率适中、误差较小、并具有较小的面积和延迟,适用于工作频率适中、对计算速度和面积要求较高的场合.

Area-Efficient integer square root algorithm was implemented to overcome the problems in a parameterized integer square root design for small bit-width. Some square data and the data ranges corresponding to their integer roots were analyzed by rounding the square root. According to the ranges, their square roots were computed in multiplex circuits. Simulation and synthesis results show that the proposed method has a moderate working frequency, smaller computation error, smaller area and latency compared with parameterized fast convergence integer square root algorithm and the square root algorithm provided by Modelsim 5.6, being suitable in the case that requires high computing speed and small areas with a proper frequency.