摘要
本文研究了双极型电路传输延时的约束机理。用灵敏度分析法导出了ＥＣＬ电路传输延时的修正公式。指出：为了提高高速数字电路的集成密度，降低单元电路的功耗是必要的。在低功耗轻负载时，ＥＣＬ电路的高速特性主要取决于电路的上拉电阻及与其相关的器件电容和引线电容。功耗越低，负载电容越大，射随器级的下拉电阻和负载电容的影响越来越占主导地位。为了克服低耗问题，文中提出了一些相应对策，并给出了一种高速低耗的可行性电路结构──改进的ＣＭＬ（ＭＣＭＬ）电路。用ｍｗＳＰＩＣＥ仿真结果表明：单门功耗为１．５４ｍＷ时，平均时延可低速１５．２ｐｓ，０．９９ｍＷ时为１７．３ｐｓ，０．４９ｍＷ时为２８．５ｐｓ。负载电容在８～８００ｆＦ范围内时，Ｐｄ（功耗－延时）积比普通ＥＣＬ电路改善２．２～３．６倍。
A study of limitation mechanisms to propagation delay of bipolar circuits has been carried out. A correctiye an.alytical propagation delay expression for ECL circuit is denyed using a sensitivity analysis. It is shown that decreasing the cell power dissipation is necessary for high ICs density. At low-pewer dissipation, the high-speed performance of un-- or light-loaded ECL circuits mainly depends on the pttll-up resistor and associated transistor capacitances as well as Wiring capacitances. Under larger capacitiye load condition, the'effects of pull-down resistor and load capacitance of the emitter-follower stage on circuit delay time get dominant as the power-dissipation gets lower. In this paper, some strategies for overcoming so-called 'lowpower problems' arc proposed, and a practicable highspeed low-power bipolar circuit structureMCML circuit is described. The computer-simulations using mwSPICE program haye shown that ayerage delays of 15 .2ps/1. 54mW, 17 .3ps/0 .99mW and 28.5ps/0 .49mW can be achieved. The power-delay product is reduced by a factor 2.2-3.6 comparied with conventional ECL gate in the range of capacitive loads from & to 800f F. The noise margin is also good.
基金
国家自然科学基金
关键词
数字集成电路
双极型电路
Emitter-coupled logic circuits
Current mode logic circuits
High-speed digital integrated circuits
