CMOS IC输入保护与抗闭锁设计

ESD Protection and Latch up Prevention in CMOS 1/O Circuit.

本文论证了CMOS IC输入保护电路抗静电耐压大多小于2000伏的重要原因在于多晶硅保护电阻烧毁。并提出新的保护电阻设计方法及综合考虑CMOS IC抗静电与抗闭锁的内在联系,从而得到了优异抗静电与抗闭锁性能的设计实践经验,绘出了在HCMOS 74HC/HCT系列产品设计中的应用结果。

This paper demonstrats main failure mode of input protections for CMOS IC is poly-silicon resistor fusion. Propose a new design of protection resistor. This papershows clearly the relation between ESD protection and a voiding latch up. Design method of protection diodes which take into account both ESD and laych up, and its practical results have been provided.