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深亚微米集成电路设计中的互连线延迟问题 被引量:2

Interconnect Wire Delay Questions in Deep Submicron IC Design
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摘要 深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。本文讨论了影响互连线延迟的因素并对深亚微米物理设计的关键步骤中如何考虑并解决互连线延迟问题进行叙述和讨论。 Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.The factors that affect the interconnect wire delay and the resolution ways in deep submicron IC design are described in this paper.
出处 《电子与封装》 2005年第3期29-32,共4页 Electronics & Packaging
关键词 深亚微米大规模集成电路 互连线 延迟 布局 布线 Deep submicron VLSI Interconnect Wire Delay Place and Route
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参考文献8

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