Viterbi译码器的FPGA设计实现与优化

FPGA implementation and optimization of Viterbi decoder

在分析Viterbi译码算法基础上,采用一种新的流水结构设计Viterbi译码器的ACS模块.合理安排幸存路径的读写,采用单指针回溯算法译码输出,最终在XilinxISE上完成了约束长度为9的Viterbi译码器的FPGA设计.仿真实验结果表明,设计的译码器在资源消耗上有较大优势.

On the basis of Viterbi algorithm, a novel pipeline architecture of ACS module and a reasonable arrangement method of survive paths are present in this paper. And the output of the decoder is based on one-pointer algorithm. The FPGA design of the decoder is implemented on Xilinx ISE .The experiment results show such design is reasonable and can save hardsware resources.