数字信号处理器综合测试方案

Integrated Test Scheme for Digital Signal Processor

该文以16位数字信号处理器测试为例,形成涵盖主要功能块的测试方案.对于指令部分,强调δ+和δ-的故障模型作为测试的重点;指令顺序先对内部寄存器读、写指令测试,然后测试其它指令;流水线指令测试按照数据条件、条件相关、转移相关的"写后读"方法进行测试;通用寄存器堆部分,结合边界扫描的MARCHB算法进行测试;中断部分,采用了全扫描链的中断测试算法;形成了整体数字信号处理器测试方案,并给出算法的测试程序、具体例子、测试程序统计结果.

Based on boundary scanning and a full scanning structure design of a 16-bit digital signal processor, different test logarithms are used for difference functional parts. The instruction test emphasizes a δ^+ and δ^- fault model. The test instructions are given in the following order. A couple of writing and reading instructions are tested first before other instructions. Pipeline instructions are tested based on the principle of 'write after read' in a data-dependent, condition-dependent, and sequence control dependent fashion. Interruption section is tested on the full scan using an interruption (algorithm.) Data transfer fault test is also considered. MARCH B algorithm is used to test ROM and RAM on the boundary scan. The test scheme of the entire digit signal processor including detailed procedures examples and statistical results of the entire procedures is given.