基于FPGA的新型Walsh码发生器的设计与实现

Design and Implementation of a New Type Walsh Code Generator Based on FPGA

介绍了一种离散Walsh函数的新型构造方法,然后给出了采用这种新方法设计的Walsh码发生器的电路框图,并给出了该设计的FPGA(现场可编程门阵列)器件实现方法,最后用VerilogHDL语言编程和QuartusⅡ开发软件进行了仿真验证。结果表明,该方法十分简便,电路结构简单,成本低,应用在CDMA(码分多址)通信系统中能明显减少带宽,提高频带的利用率,实用性好。

In this paper, we introduce a new generator of discrete Walsh function. According to the new design method, the block diagram of the new Walsh functional sequence generator is designed, and the design of FPGA devices is discussed. Finally, simulated verification is made using Verilog HDL language and the software of QuartusⅡ. Results show that the new method can simplify the design and reduce cost. Discrete Walsh function can be used in the CDMA communication system to decrease significantly bandwidth, andimprove efficiency of channel band using. In conclusion, it is shown that the new generator of Walsh code has good practical usability.