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一种稳定的RLC互连π模型构建及其应用 被引量：1

A Stable Construction of RLC Interconnect π Model and Its Application 
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摘要 基于RLC互连树节点导纳的低阶矩构建了一种稳定的互连π模型,并讨论了它在互连树延时和逻辑门延时估计中的应用.结果表明,该模型与已有方法相比精度有一定程度的提高. This paper constructs a stable RLC interconnect π model based on the first three moments of the node admittance,and discusses its application to interconnect delay and logic gate delay estimation.Results show that the accuracy is considerably increased compared with the methods available.
作者 董刚 高海霞 杨银堂 李跃进
机构地区 西安电子科技大学微电子研究所
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第3期580-584,共5页 半导体学报（英文版）
基金 国防科技预研资助项目(No.41323020204)~~
关键词 RLC互连树 节点导纳 逻辑门 延时 RLC interconnect tree node admittance logic gate delay
分类号 TN405.97 [电子电信—微电子学与固体电子学]
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参考文献10

  • 1Ismail Y I,Friedman E G,Neves J L.Equivalent Elmore delay for RLC trees.IEEE Trans on CAD,2000,19(1):83.
  • 2Kashyap C V,Krauter B L.A realizable driving point model for on-chip interconnect with inductance.Proc DAC,2000:190.
  • 3Qian J,Pullela S,Pillage L.Modeling the effective capacitance for the RC interconnect of CMOS gates.IEEE Trans on CAD,1994,13(12):1526.
  • 4Devgan A,O'Brien P R.Realizable reduction of RC interconnect circuits.Proc ICCAD,1999:204.
  • 5El-Moursy M A,Eby G.Friedman,Shielding effect of on-chip interconnect inductance.Proc ACM Great Lakes Symposium on VLSI,2003:165.
  • 6Yang Xiaodong,Cheng C K,Ku W H,et al.Hurwitz stable reduced order modeling for RLC interconnect trees.Proc ICCAD,2000:222.
  • 7Brocco L M,McCormick S P,Allen J.Macro-modeling CMOS circuits for timing simulation.IEEE Trans on CAD,1988,7(12):1237.
  • 8Weste N H,Eshraghian K.Principles of CMOS VLSI design.New York:Addson Wesley,1993.
  • 9董刚,杨银堂,李跃进.驱动复杂RLC互连树的逻辑门延时[J].Journal of Semiconductors,2004,25(8):1036-1040. 被引量：2
  • 10Kahng A B,Muddu S.Efficient gate delay modeling for large interconnect loads.Proc IEEE Multi-Chip Module Conf,1996:202.

二级参考文献8

  • 1Pillage L T,Rohrer R A. Asymptotic waveform evaluation for timing analysis. IEEE Trans Comput-Aided Des Integr Circuits Syst,1990,9 (4):352
  • 2Feldman P,Freund R. Efficient linear circuit analysis by Pade approximation via the Lanczos process. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1995,14 (5): 639
  • 3Kashyap C V,Krauter B L. A realizable driving point model for on-chip interconnect with inductance. Proc DAC 2000:190
  • 4Qian J,Pullela S,Pillage L. Modeling the ''effective capacitance'' for the RC interconnect of CMOS gates. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1994,13 (12) : 1526
  • 5Devgan A,O'Brien P R. Realizable reduction of RC interconnect circuits. Proc ICCAD, 1999 : 204
  • 6El-Moursy M A, Friedman E G. Shielding effect of on-chip interconnect inductance. Proc ACM Symposium on Great Lakes Symposium on VLSI, 2003 : 165
  • 7Kahng A B,Muddu S. Efficient gate delay modeling for large interconnect loads. Proc IEEE Multi-Chip Module Conf,1996:202
  • 8http:∥public. itrs. net/files/2000UpdateFinal/2kUdFinal.htm

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Journal of Semiconductors
2005年 第3期

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