摘要
本文研究了8B/10B编码规则及其内在相关性,提出了一种查表和逻辑运算相结合的新的8B/10B编、解码方法,具有运算量小、编解码同步好、速度快、可靠性高等优点。该方法通过硬件描述语言Verilog HDL实现编解码算法的描述,并通过高性能的FPGA器件进行仿真和综合,实现了具体的硬件电路,并验证了设计方法的有效性和可行性。采用该方法可实现不同速率的高速8B/10B编解码模块或芯片的设计。
The encoding rule of 8B/10B and inherent relationship among 8B/10B codes are studied in this paper. A new implementing method of 8B/10B encoding and decoding is introduced, which combines the advantages of lookup-table and logic analysis methods with low computation complexity, easy synchronization, high speed and high reliability. The algorithm of encoding and decoding is described with Verilog HDL, and was simulated and synthesized with high performance FPGA. So the hardware circuit is realized to validate the feasibility of this method. The design of different high speed 8B/10B encoding and decoding module or IC is easily fulfilled with it.
出处
《电路与系统学报》
CSCD
北大核心
2005年第2期30-34,共5页
Journal of Circuits and Systems
基金
国家863计划资助项目(2002AA312240
2003AA312040)
关键词
8B/10B码
编码
解码
光纤通信
集成电路
8B/10B code
encoding
decoding
fiber communication
integrated circuit