基于双边沿触发计数器的低功耗全数字锁相环的设计

Design of low power all digital phase-locked loop based on double edge triggered counter

提出了一种低功耗、快速锁定全数字锁相环的设计方法。该文从消除因时钟信号冗余跳变而产生的无效功耗的要求出发,阐述了双边沿触发计数器的设计思想,提出了用双边沿触发计数器替代传统数字序列滤波器中的单边沿触发计数器的锁相环设计方案,以从降低时钟工作频率、减小工作电压和抑制冗余电路的开关活动性等方面降低系统的功耗;同时在环路中采用自动变模控制技术,以加快环路的锁定速度,减少相位抖动。最后采用EDA技术进行了该全数字锁相环的设计与实现,理论分析和实验结果表明其低功耗性、快速锁定性均有明显改善。

A design method for all DPLLs that with low power cost and high phase locked velocity has been proposed. Starting from the demand of eliminating inefficient power dissipation that caused by the redundant toggles of the clock and circuit itself, we firstly set forth the design ideas of double edge triggered (DET) counter, and then propose an all DPLL design scheme that adopts DET counter instead of conventional single edge triggered (SET) one. Thus system power dissipation has been evidently reduced by lowering frequency of system clock and voltage of power supply and restraining on-off activities of redundancy circuits. At the same time, a variable module control algorithm was adopted in the loop to enhance its lock velocity and reduce phase twittering. Finally, an all DPLL was designed and implemented by EDA technology. Both theoretic analysis and experiment results demonstrate that power dissipation of the all DPLL system based on this type of DET counter can be evidently reduced and its phase locked velocity can be consumedly enhanced as well.