基于CTL的SOC IP核的测试技术

CTL-Based SOC IP Core Test Design

本文介绍了一种针对SOC测试设计中嵌入式芯核的核测试语言(CTL)。该语言描述了如何将可测试性设计置入具有知识产权 (Intellectual Property,简称 IP)芯核和SOC中,从而加速测试生成和复用。CTL语言标准虽然还未被IEEE正式通过,但已经在EDA厂商、ATE厂商和 IP芯核提供者之间悄然兴起并被积极采用,一系列基于 CTL的产品也相继被研制出来。本文通过对CTL的分析与研究,较为详细地说明了 CTL引入的重要性及其特性,并为 SOC IP芯核提供CTL语言测试设计实例。

This paper presents a core test language(CTL) of SOC IP(Intellectual Property) core design .This language provides a standard description of how to insert DFT (Design for Test) into the IP cores and the SOC (System-on-Chip) in order to accelerate test generation and reuse. Although the IEEE P1450.6 Core Test Language (CTL) has not been adopted yet, a complete design-through-test solution based on CTL is already available to the industry. To make this point, this paper will explore the P1450.6 in greater detail including an organizing paradigm for CTL data.