摘要
随着Memory的集成度越来越高,逻辑参数的提取时间变得无法忍受。在分析Memory结构特点和工作特性的基础上,提出了一种Memory逻辑参数提取的新方法。方法根据AWE模型简化了电路中的RC数量,依据激励波形简化电路中的不活动部分。研究表明新方法能很好地保持电路原有的功能特性和电气特性并大大加快了提取速度。
As Memory circuit densities increase, the extraction time of logic parameter is beginning unendurable. The paper presents a new method based on circuit reduction for Memory logic parameter extraction. It can reduce the number of RC according to AWE model, and cut the inactive part circuit according to the stimulate wave. The studies show that it can keep very well the function feature and the electrical feature, and it reduces appreciably the extraction time.
出处
《微电子学与计算机》
CSCD
北大核心
2005年第3期255-258,共4页
Microelectronics & Computer
关键词
逻辑参数
寄生参数
电路简化
Logic parameter, Parasitic parameter, Circuit reduction