如何选择正确的验证方法

How to Choose a Verification Methodology

本文对时下流行的验证技术(形式验证、随机、定向、有约束的随机、断言、属性检验)与语言(SystemC、C/C++、SystemVerilog、Open-VERA、E等)进行了全面评述,并分析了在传统的数字ASIC设计流程中应当在何时采用何种验证技术和语言。

This article gives the reader an overview of the prevalent verification techniques (formal verification, random, directed, constrained random, assertions, property checking) and languages (SystemC, C/C++, SystemVerilog, Open-VERA, E, etc). It also examines the place for the various verification techniques and a time during a traditional digital ASIC design flow.