高速数据采集系统时钟抖动研究

Clock Jitter Study of High Speed Data Acquisition Systems

研究了数据采集系统时钟抖动、ADC量化噪声以及ADC微分非线性与信噪比的关系.通过合理的假设,利用自相关和功率谱密度的关系,推导出了信噪比与抖动和噪声的数学公式.并建立仿真模型,验证该公式.结果表明,在输入信号频率比较高的时候,信噪比以20 dB/倍频下降,时钟抖动决定了20 dB/倍频下降的起始位置.

In this paper, the effect of sampling clock, the quantization noise and DNL of ADC on SNR are investigated from a practical perspective. Based on a reasonable proposition, a powerful expression for the SNR is derived with generic autocorrelation and input signal. A simulation model used to verify the SNR expression is proposed.