模拟集成电路三维互连电容的改进层次式提取

Improved Hierarchical Extraction of 3D Interconnect Capacitance in Analog Integrated Circuits

层次式直接边界元方法可一次性计算出整个互连寄生电容矩阵,具有较高的计算效率针对模拟集成电路的特点,对层次式三维电容提取的三维块切割方式、非均匀边界元划分和程序组织等方面进行了改进,显著地提高了算法的效率数值实验表明,改进的层次式互连电容提取在保证高精度的同时,速度提高了数倍。

The hierarchical block boundary element method is highly efficient by its once computation to extract the whole interconnect capacitance matrix. In analog integrated circuit layout, the feature size varies largely with different layers. According to this, we present an improved algorithm in this paper, including a new hierarchical partition method of 3D blocks, nonuniform subdivision of boundary elements, and optimization of algorithm organization. Numerical results show that the new algorithm is suitable for real analog integrated circuit layout, in an improvement under equal accuracy, a few times faster than the previous approach.