基于FPGA的16阶FIR滤波器的设计

Design of 16 order FIR filter based on FPGA

研究了一种 16阶FIR滤波器的FPGA设计方法,底层采用VHDL语言描述设计文件,顶层使用底层产生的模块连接组成FIR滤波器,并在MAX+plusII上进行了实验仿真和时序分析。对如何优化硬件资源利用率、提高运算速度等工程实际问题进行了探讨。

To study method to implement 16 order FIR filter based on FPGA, FIR filter is described with VHDL language and the mode of skeleton diagram. And it is simulated experementally and timing analysis proceeds in MAX+plus II.With the design, how to accelerate the operation and optimize the availability of hardware resource are discussed.