1[1]Wuudiann Ke,Khoan Truong.Design with testability for a platform-based SOC design methodology.ASICs,1999.AP-ASIC′99.The First IEEE Asia Pacific Conference on,1999:307～310
2[2]Kosonocky S V,Bright A,Warren K,etal.Designing a testable system on a chip.VLSI Test Symposium,1998,Proceedings.16thIEEE,1998:2～7
3[3]Needham W M.Nanometer technology challenges for test and test equipment. Computer,1999;32(11):52～57
