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一种改进的SMT模拟器——支持Oracle机制和多种取指策略

An Improved SMT Simulator——Supporting Oracle Mechanism and Multiple Fetch Policies
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摘要 模拟器是计算机系统设计中非常重要的一种技术。O racle研究能够用来确定所研究问题的最优或最差情况,为正常研究提供有用的辅助信息。但是现在常用的一些同步多线程(SM T)模拟器都不能提供支持O racle研究所需的信息。文章结合原有模拟器的基础,提供了一种新的支持O racle研究的模拟平台。同时原SM T模拟器只支持ICO UNT这一种取指策略,文章在原模拟器基础上,又增加了BR COU NT和M ISSCO UNT这两种通用的取指策略。 Computer simulation is a vital technology in the computer system design.Oracle study can make certain the best and worst circumstance of the researched problem,and can provide some useful assistant information.However,many popular Simultaneous Multi-Threading(SMT)simulators can't provide extensive support for Oracle studies.This paper proposes a novel SMT infrastructure that is well-suited for Oracle studies.Meanwhile,original SMT simulator provides only one fetch policy,which is ICOUNT.So BRCOUNT and MISSCOUNT are added to this new simulation infrastructure as additional fetch policies.
出处 《计算机工程与应用》 CSCD 北大核心 2005年第14期57-60,共4页 Computer Engineering and Applications
基金 国家自然科学基金项目(编号:60103002)
关键词 同步多线程 模拟器 Oracle研究 取指策略 Simultaneous Multi-Threading(SMT),simulator,Oracle studies,fetch policies
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参考文献13

  • 1S J Eggers,J S Emer,H M Levy et al. Simultaneous multithreading:A platform for next-generation processors[C].In:IEEE Micro, 1997-10:12~19.
  • 2D M Tullsen,S J Eggers,J S Emer et al. Exploting choice:Instruction fetch and issue on an implementable simultaneous multithreading processor[C].In:23rd Annual International Symposium on Computer Architecture, 1996-05:191~202.
  • 3R Desikan, D Burger ,S Keckler. Measuring Experimental Error in Microprocessor Simulation[C].In:Proc of the 28th Annual Int Symposium on Computer Architecture,2001-07.
  • 4D Burger,T Austin.The Simplescalar Tool Set[R].Version 2.0,In Technical Report CS-TR-97-1342,Univ of Wisconsin,Madison,1997 -06.
  • 5R L Sagula,T Diverio. Modelagem Analitica:Formalismos e Ferramentas[C].In :Trabalho Individual 789, PPGC/UFRGS, 1999.
  • 6R A L Goncalves et al,SEMPRE:A Superscalar Architecture with Multiple Processes in Execution[C].In:X SBAC-PAD,Brazil,1998-09.
  • 7R A L Goncalves et al.A Simulator for SMT Architectures:Evaluating Instruction Cache Topologies[C].In: ⅩⅡ SBAC-PAD, Brazil,2000-10.
  • 8R A L Goncalves et al. Improving SMT Performance Scheduling Processes[C].In:Proceedings of the 10th Euromicro Workshop on Parallel, 2002.
  • 9C Lindemann. Performance Modeling with Deterministic and Stochastic Petri Nets[M].John Wiley and Sons,1998.
  • 10D M Tullsen,S J Eggers,H M Levy. Simultaneous multithreading:Maximizing on-chip parallelism[C].In :the 22nd Annual International Symposium on Computer Architecture, 1995:392~403.

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