期刊文献+

面向DSP应用的可重构计算(英文) 被引量:2

Reconfigurable Computing Exploration for DSP Applications
下载PDF
导出
摘要 DSP应用的特点是计算密集并适合并行处理,传统的可编程处理器与ASIC在性能和灵活性上各有优劣。因此出现了一种新的计算模式—可重构计算。由于它能将效率和灵活性很好地结合在一起,故正得到广泛的关注和研究。本文在介绍可重构计算的概念和分类的基础上,着重讨论了一些主流的可重构计算系统,分析了各类系统应用于DSP的特点,对可重构计算在计算模型,编译器,映射技术以及开发环境等方面的现状和趋势进行了探讨,并给出了自己的思考。 Within the DSP applications, which are computationally intensive and desirable for parallel processing, programmable processors and ASICs have their own advantages and defects respectively. Consequently a new computing paradigm-reconfigurable computing has received wide attention and under extensive researches due to its ability to combine the efficiency with flexibility. The paper introduces the basic concept and taxonomy of reconfigurable computing, describes some main-stream reconfigurable systems and analyzes their characteristics. Then the paper discusses the challenges and directions in developing computation models, compiler, mapping technique, as well as entire development environment for the reconfigurable architectures, and draws the conclusions.
出处 《微电子学与计算机》 CSCD 北大核心 2005年第4期45-50,共6页 Microelectronics & Computer
基金 国家自然科学基金资助(60273088)
关键词 可重构计算 DSP ASIC 可编程处理器 Reconfigurable computing, DSP, ASIC, Programmable processor
  • 相关文献

参考文献22

  • 1G R Goslin. A Guide to Using Field Programmable Gate Arrays for Application-Specific Digital Signal Processing Performance. In Proceedings of SPIE, vol. 2914: 321~331.
  • 2K Bondalapati, V K Prasanna. Reconfigurable Computing Systems. Proceedings of the IEEE, July 2002,90(7): 1201~1217.
  • 3J Hauser and J Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor. In IEEE Symp. FPGA's for Custom Computing Machines, Apr. 1997: 12~21.
  • 4Chameleon Systems [Online]. Available: http://www.chameleonsystems.com/.
  • 5J R Hauser, J Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Co-Processor. Proc. IEEE. Symp. FieldProgrammable Custom Computing Machines, Apr. 1997.
  • 6E Mirsky, A DeHon. MATRIX:A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources. Proc. IEEE Symp. FPGAs for Custom-Computing Machines, Apr. 1996: 157~166.
  • 7A K Yeung and J M Rabaey. A 2.4 GOPS Data-Driven Reconfigurable Multiprocessor IC for DSP. Proc. IEEE Solid-State Circuits Conf., Feb. 1995:108-109, 346, 440.
  • 8T Miyamori, K Olukotun. A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications.Proc. IEEE Symp. FPGAs for Custom Computing Machines, Apr. 1998.
  • 9J Babb, M Frank and V Lee. The RAW Bechmark Suite:Computation Structures for General-Purpose Computing.Proc. IEEE Symp. Field-Programmable Custom Computing Machines, Apr. 1997:134~143.
  • 10D Chen and J Rabaey. A Reconfigurable Multi-Processor IC for Rapid Prototyping of Algorithmic-Specific HighSpeed Data-paths. IEEE K. Solid-State Circuits, Dec.1992: 27(12).

同被引文献9

  • 1袁涛,樊晓桠,荆元利.面向并行DSP应用的双路由多层Mesh结构研究[J].计算机工程与应用,2007,43(6):88-91. 被引量:2
  • 2林明亮,祝永新.基于SimpleScalar的异构多核仿真器[J].微电子学与计算机,2007,24(7):204-208. 被引量:7
  • 3David E Culler.并行计算机体系结构[M].北京:机械工业出版社,2003.
  • 4Jordan Harry F.并行处理基本原理[M].北京:清华大学出版社,2004.
  • 5Raasch Reinhardt S.The impact of resource partitioning on SMT processors[A].In Proceedings of the 12th International Conference of Parallel Architectures and Compilation Techniques[C].September 2003:15~26
  • 6McNairy C,Bhatia R.Montecito:A dual-core,dual-thread itanium processor[J].IEEE March,2005,25(2):10~20
  • 7Kongetira P,Aingaran K,Olukotun K.Niagara:A 32-way multithreaded sparc processor[J].IEEE Micro,2005,25(2):21~29
  • 8El-Moursy A,Garg R,Albonesi D H,et al.Compatible phase co-scheduling on a CMP of multi-threaded processors[C].20th International Parallel and Distributed Processing Symposium,2006:10~22
  • 9Edward Suh G,Srinivas Devadas,Larry Rudolph,A new cache monitoring scheme for memory-aware scheduling and partitioning[C].HPCA-8:1,2002:100~107

引证文献2

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部