摘要
USB2.0协议规定了高速模式下的数据传输速度为480Mbps,可满足图像、音频信号等数据传输的要求。本文论述了USB2.0中链路层数据的传输机制和高速数字硬件模块功能,提出了一种新颖的基于全数字锁相环(ADPLL)的全速模式数据恢复电路,以及为满足480Mbps传输速度的高速编解码的并行设计方法。设计采用TSMC0.25μmCMOS工艺库。电路的前后仿真结果表明设计的电路达到了480MHz的处理速度,并在FPGA上进行了功能验证。
The USB2.0 supports the high-speed signaling at 480 Mbps. It can meet the needs of image and voice signal transmitting. In this paper, after demonstration of the characters and functions of high speed digital circuit of USB2.0 link layer, a novel design and implementation method of data recovery circuits, which is based on all digital phase-looked loop (ADPLL), for the full-speed mode, as well as a new approach of parallel implementation of the encode/decode module in high-speed mode were proposed. The simulation results indicated that the circuit has reached 480MHz. A FPGA hardware simulation system was developed, in which the functions of link layer was verified.
出处
《微电子学与计算机》
CSCD
北大核心
2005年第4期137-139,143,共4页
Microelectronics & Computer
基金
国家863高科技计划项目(2002AA121320)
