LS-DSP数字信号处理器总线的低功耗设计

The Low Power Design of the Bus for Digital Signal Processor LS-DSP

随着数字信号处理器制造工艺的进步,总线的功耗已经成为数字信号处理器功耗的主要组成部分。研究了LS DSP数字信号处理器地址总线、数据总线、内部数据总线三类总线的低功耗设计技术,主要采用了总线编码的方法实现总线的低功耗。实验结果表明,LS DSP采用总线低功耗技术后,有效地降低了总线的功耗。

With the development of fabricate technology for di gital signal processor(DSP), the power dissipation of the bus is the main part o f the wh ole power dissipation in DSP. This paper researches the power saving ways for ad dr ess bus?data bus?internal bus in LS-DSP . Bus coding technology has been u sed for that purpose. The experimental results show that the LS-DSP bus power can reduce effectively when it uses the power saving ways discussed in this pape r are used.