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Integrating advanced reasoning into a SAT solver 被引量:2

Integrating advanced reasoning into a SAT solver
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摘要 In this paper, we present a SAT solver based on the combination of DPLL (Davis Putnam Logemann and Loveland) algorithm and Failed Literal Detection (FLD), one of the advanced reasoning techniques. We propose a Dynamic Filtering method that consists of two restriction rules for FLD: internal and external filtering. The method reduces the number of tested literals in FLD and its computational time while maintaining the ability to find most of the failed literals in each decision level. Unlike the pre-defined criteria, literals are removed dynamically in our approach. In this way, our FLD can adapt itself to different real-life benchmarks. Many useless tests are therefore avoided and as a consequence it makes FLD fast. Some other static restrictions are also added to further improve the efficiency of FLD. Experiments show that our optimized FLD is much more efficient than other advanced reasoning techniques.
出处 《Science in China(Series F)》 2005年第3期366-378,共13页 中国科学(F辑英文版)
基金 supported by the National Natural Science Foundation of China(Grant Nos.90207002 and 60176017) the National High Technology Research and Development 863 Plan(Grant Nos.2002AAIZ1460,2002AA1Z1340 and 2002AA1Z1460) NSF(Grant Nos.CCR-0098275 and CCR-0306298).
关键词 satisfiability (SAT) formal verification electronics design automation. satisfiability (SAT), formal verification, electronics design automation.
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