基于RTL级实现的可综合的16×16位带符号/无符号高速乘法器

A16×16-b Signed/Unsigned Synthesizable High-Speed Multiplier in high-level RTL code

本文提出了一种综合使用改进后的Booth编码算法、Wallace树形结构、先行进位加法器,利用HDL进行RTL级的乘法器的设计,因而可以方便地应用于不同的工艺库。逻辑设计与工艺设计是互不相关的。设计的代码经过仿真和综合后表明,采用TSMC0.18μm的工艺库在温度为25℃、电源电压为1.8V的情况下,最小延迟为3.5ns,在时钟频率为200MHz时,芯片面积为26277.0957μm2,平均功耗为7.123mW。

This paper presents a new multiplier,which makes use of modified signed/unsigned Booth encoder, Wallace tree and Carry Look-ahead adder. We design it by HDL in high level RTL code.So it can be suitable to any process.Logic design techniques are independent of process technology. Using the TSMC 0.18 μm process, simulation and synthesis of the RTL code showed that critical path of multiplication is 3.5ns at a supply voltage of 1.8V and a temperature of 25 degrees centigrade, and the area is 26277.095 7 μm2, the average power dissipation is 7.123mW at a frequency of 200MHz.