基于精确时延模型考虑缓冲器插入的互连线优化算法

Simultaneous Routing and Buffer Insertion Under Fixed Buffer Locations Based on Accurate Delay Models

随着VLSI电路集成度增大和特征尺寸的不断减小,连线的寄生效应不可忽略,互连线的时延在电路总时延中占了很大的比例,成为决定电路性能的主要因素.在互连时延的优化技术中,缓冲器插入是最有效的减小连线时延的方法.本文提出了一个在精确时延模型下,在布线区域内给定一些可行的缓冲器插入位置,对两端线网进行拓扑优化,并同时插入缓冲器以优化时延的多项式时间实现内的算法.我们的算法不但可以实现时延的最小化,也可以在满足时延约束的条件下,最小化缓冲器的插入数目,从而避免不必要的面积和功耗的浪费.

For VLSI designs under deep submicron technology, it is well known that interconnect delay has become dominant factor in determining the overall circuit performance. Buffer insertion is an efficient technique for interconnect optimization. This paper presents an algorithm of routing and inserting buffers simultaneously to reduce wire delay for a two-pin net under fixed buffer locations based on accurate delay models. Given a two-terminal net, the algorithm can not only minimize the total delay time of the net, but also minimize the number of buffers inserted to meet a given delay constraint, thus avoid needless power and area cost.