VHDL语言在数字电路中的设计与应用

Design and Application of VHDL in Digital Circuit

根据教学实践,介绍了VHDL硬件描述语言进行工程设计的优点。他既是一种与实际技术相独立的语言,不束缚于某一特定的模拟程序或数字装置上,也不把设计方法强加于设计者,他允许设计者在其使用范围内选择工艺和方法,描述能力极强,覆盖了逻辑设计的诸多领域和层次,并支持众多的硬件模型;也是一种在数字电路教学中全新的理论联系实际的教学方法和全新的培养学生实际动手能力的有效工具。同时简要地说明VHDL硬件描述语言的支撑软件Max+PlusⅡ。并结合实例详细阐明VHDL语言在Max+PlusⅡ软件的环境下对数字电路的设计、应用方法及使用时需注意的几个方面事项。

In this paper, the advantage of using VHDL for project design is described. VHDL is independent of analog program and digital apparatus, it permits the designer to determine the technology and method within certain limits, it has powerful description ability and can describe digital system at all levels. Many hardware models are applied to it. So it is effective for combining theory with practice during teaching and cultivating the operating ability of students. The software Max+Plus Ⅱis introduced in this paper. In addition, the way of digital logic design and application using VHDL is presented by giving examples, and points for attention are elaborated.