基于FPGA的快速加法器的设计与实现

Design and Implementation of High-speed Adder Based on FPGA

加法器是算术运算的基本单元,可以有多种实现结构,采用不同的结构实现其耗用的资源和运算的速度也各不相同。本文研究了基于FPGA的常用加法器的结构及其设计方法,对各自性能加以分析比较,在此基础上采用流水线结构设计了一个8位的加法器。并在Xilinx公司的ISE 5 .2 i软件环境下,采用VHDL和Verilog HDL硬件描述语言进行了设计实现并使用Modelsim进行仿真验证,在此基础上对其性能进行了比较分析。实验结果表明流水线加法器的速度高于其他结构实现的加法器。

Adder is the basic cell of arithmetic operation, many structures can be used to implement it, and the adder designed by different method consumes different number of resource and has a different speed respectively. This paper studies the structures and methods of adder based on the FPGA, analyses and compares the performance of each adders, moreover design a 8b adder based on the structure of pipeline. Carry out it by utilizing the Hard Describe Language (VHDL and Verilog HDL) and ISE software package V5.2i from Xilinx and simulating it by Modelsim software, and evaluation and comparison the performance (area and speed) of it. The result of experiment indicates that the pipeline adder is faster others.