摘要
在锁相环设计中,双模前置分频器(dual-modulusprescaler)是一个速度瓶颈,而D触发器是限制其速度的主要因素。我们对传统的Yuan-Svensson真正单相时钟(TSPC)D触发器(DFF)做了改进,给出了动态有比D触发器的结构,该触发器结构简单,工作频率高,功耗低。并基于此设计了一个可变分频比双模前置分频器,可适用于多种无线通信标准。采用0.35μmCMOS工艺参数进行仿真,结果表明,在3.3V电源电压下其工作频率可达4.1GHz。
In PLL design, dual-modulus prescaler is one of the bottlenecks in achieving a higher operation speed, and D flip-flop is the key factor limiting the speed of prescaler. A modification of the conventional Yuan-Svensson TSPC D flip-flop is made, and the structure of dynamic ratioed flip-flop is presented. This flip-flop is simple and could work at very high frequency, low power. Based on this technique a programmable dual-modulus prescaler is designed, and can be applied to several different wireless communication standards. The simulation results in 0.35 μm CMOS process show that the maximum input frequency is 4.1 GHz at the power supply of 3.3 V.
出处
《电子器件》
CAS
2005年第2期398-400,403,共4页
Chinese Journal of Electron Devices
关键词
锁相环
频率合成器
前置分频器
D触发器
PLL(phase locked loop)
frequency synthesizer
prescaler
D flip-flop
