摘要
介绍了一种三通道高速数据采集与脉冲压缩系统的研究与实现。系统使用AD13465实现14位32MSPS数据采集,使用FPGA实现1024点和256点可变点数脉冲压缩。脉压模块采用双蝶形运算单元并行处理,其中的基4蝶形运算单元可同时完成FFT、复乘和IFFT运算,使硬件的规模减少到正常情况下的1/3。系统采用块浮点算法以提高动态范围。脉压结果使用32位IEEE754/854浮点格式输出。整个芯片完成1024点和256点脉压时间最快分别为57.70μs和12.65μs。
A high-speed tri-channel data acquisition and pulse compression system is studied and implemented. AD134 65 is used for 14 bits,32 MSPS data acquisition, and FPGA is used for digital pulse compression(DPC). The dual-butterfly DPC module with an improved radix-4 butterfly can perform not only FFT, but also Complex multiplication(CM) and IFFT. This novel structure reduced the hardware size to one-third, compared to the traditional design method. The Block-floating-point algorithm is applied to enhance data dynamic range. The DPC output is in 32-bit IEEE754/854 floating-point format which is achieved in 57.70 μs for 1 024-point DPC or in 12.65 μs for 256-point DPC.
出处
《现代雷达》
CSCD
北大核心
2005年第6期32-35,38,共5页
Modern Radar
