纳米级MOSFET器件模拟的载流子输运模型

The Carrier Transport Model of Nano-Scale MOSFET Device Simulation

随着半导体微细加工技术的发展,预计硅SOC的集成度可达万亿个晶体管,单个晶体管的尺寸将达到10nm范围内。因此从理论上研究纳米尺寸器件的性能和特性对发展超大规模集成电路尤为重要。综述了纳米级MOSFET器件数值模拟的量子模型,以及在该模型下用到的几种载流子输运模型,并结合模拟结果对这一模型作了评价。

During the progress of semiconductor micro fabrication technology, the VLSI technology requires that the characteristic scale of semiconductor device will be further reduced. The silicon technology has an enormous remaining potential to achieve terascale integration(TSI) of more than 1 trillion transistors per chip. In this case, the scale of transistor will reach 10-nm range. It is very important to study the characteristic and capability of nanodevice for the development of VLSI technology. In this article, we have reviewed the numerical simulation of nano-scale MOSFET in the theory framework of quantum transport model, moreover, several models of carrier transport under this model have been discussed. We also evaluate the result from these models.