FIFO在多级滤波图像处理ASIC芯片中的设计应用

Design of FIFO applied in the ASIC chip of image processing based on multilevel filter

描述了多级滤波图像处理ASIC芯片的体系结构,针对该芯片的数据缓冲存储问题,通过控制模块对一个输入FIFO和三个输出FIFO的协调控制,高效地实现了多路数据的实时处理和传输。结合应用要求,一个异步FIFO对输入数据缓冲存储,使快速数据通道与慢速数据输入相匹配;三个同步FIFO,分别对应单级1×3、两级1×3级联(相当于1×5)和三级1×3级联(相当于1×7)滤波模板的图像数据输出缓存,分时复用一路输出总线。仿真结果表明设计是正确且有效的。

The architecture of the multilevel filter ASIC chip used for image processing is described. There are one input FIFO and three output FIFO controlled by the control module to realize multiplex image data real time processing and transferring efficiently. Considering FIFOs' design and application in the chip, one asynchronous FIFO buffers and stores input data to match datapath to slower data import; three synchronous FIFOs are designed separately as buffer storages of image processing data from three level filter, whose templates are separately 1×3 1×5 (equates to the cascade connection of two 1×3 templates)and 1×7(equates to the cascade connection of three 1×3 templates).The three FIFOs occupy an output data bus by the way of time - sharing.Simulation results indicate that the design is right and effective.