一种通用的基四Viterbi算法的实现

a General Implementation of Viterbi Algorithm with Radix-4

文章使用基四的ACS单元来设计高速、低功耗Viterbi译码器。相对于基二的ACS单元,其复杂度提高了一倍。因此,针对于具体FPGA硬件实现,将算法进行了优化,使得更适合于硬件实现。实际结果表明,优化后的算法使得器件资源减少了,复杂度降低了,而且系统性能也得以提升。

In this paper,a fast and low power consumption Viterbi decoder is implemented with radix-2 ACS unit.As to the specific implementation with FPGA,the algorithm is optimized to fit in with the device.The result shows the optimized algorithm makes the resources reduced,complexity become lower and the performance of the system improved.