期刊文献+

边界扫描测试技术的原理及其应用 被引量:12

Principle and Application of Boundaryscan Test Technology
下载PDF
导出
摘要 边界扫描技术是一种应用于数字集成电路器件的标准化可测试性设计方法,他提供了对电路板上元件的功能、互连及相互间影响进行测试的一种新方案,极大地方便了系统电路的测试。自从1990年2月JTAG与TEEE标准化委员会合作提出了“标准测试访问通道与边界扫描结构”的IEEE1149.11990标准以后,边界扫描技术得到了迅速发展和应用。利用这种技术,不仅能测试集成电路芯片输入/输出管脚的状态,而且能够测试芯片内部工作情况以及直至引线级的断路和短路故障。对芯片管脚的测试可以提供100%的故障覆盖率,且能实现高精度的故障定位。同时,大大减少了产品的测试时间,缩短了产品的设计和开发周期。边界扫描技术克服了传统针床测试技术的缺点,而且测试费用也相对较低。这在可靠性要求高、排除故障要求时间短的场合非常适用。特别是在武器装备的系统内置测试和维护测试中具有很好的应用前景。本文介绍了边界扫描技术的含义、原理、结构,讨论了边界扫描技术的具体应用。 Boundary scan technology applied to the digital integrate circuits is an integrated and standardized method to the problem of test.It provides a solution to the test of componentfunctionality,board interconnection and interaction,which facilitates the debugging of system circuitry.Since JTAG/IEEE Standardization Committee proposed jointly the IEEE1149.11990 Std the standard Test Access Port and the Boundary Scan architecture ,Boundary Scan technology has developed rapidly and has been applied extensively.Utilizing this technology we can not only test the status of input/output pins of integrate circuit chip,but also test the interior function and even the fault of downlead level turn off and short circuit.For testing chip pins,the fault coverage can reach 100%,and the fault position can be positioned with high accuracy.At the same time,the time of position testing products is reduced greatly,the design and development cycle is shortened.Boundary Scan technology overcomes the defect of traditional neilsbed test technology,and the test cost is relatively lower.This technology is very suitable for the occasion on which we need high reliability and the short time of eliminating fault.Especially this technology will have a very good application prospect in the Intest of weapons and equipments and in maintenance test.In the paper,theory and architecture of BST will be introduced,then its application will be discussed.
出处 《现代电子技术》 2005年第11期20-24,共5页 Modern Electronics Technique
关键词 边界扫描 边界扫描测试技术 印刷电路板 联合测试行动组 集成电路 boundary scan boundaryscan test technology PCB JTAG IC
  • 相关文献

参考文献8

二级参考文献7

  • 1崔向东.JTAG边界扫描机制及应用[J].计算机工程与科学,1996,(1).
  • 21.Pat McHugh.IEEE P1149.5 Standard Module Test and Maintenance Bus.Autotestcon'93
  • 32.Lee Nayes,Larry Lauenger.Adding Boundary Scan Test Cability to an Existing Multi-Strategy Tester,Autotestcon'93
  • 43.Jayal Lakhani.Design of Hierarchical Testable Digital Architecture,Autotestcon'93
  • 54.Ungar L Y.Built-in Test IC Provides Automatic Test Equipment Capabilities,Autotestcon'91
  • 65.Milgram J D.Automated Boundary-Scan Diagnostics:Adding Value to Interconnect Testing,Autotestcon'92
  • 7崔向东,计算机工程与科学,1996年

共引文献21

同被引文献59

引证文献12

二级引证文献19

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部