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一种扩展部分BCH码纠错能力的方法 被引量:4

Method of extending error-correcting capability of some BCH codes
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摘要 提出一种简单的查表译码算法以扩展某些BCH码的纠错能力.首先搜索出BCH(n,k,t)码能够纠正的码重为t+1的错误图样,再将这些错误图样与码重小于t+1的错误图样放在一起,根据它们对应的伴随式大小进行排序,优化存储于硬件设备中,从而进行查表法译码.仿真表明:对于BCH码,采用这种译码方法,在相同的码长和信息比特数的条件下,能够比一般的BCH译码方法纠正更多错误,而且译码电路相对简单,译码速度快.这种提高纠错能力的译码方法对所有的二进制线性循环码都是适用的. A simple decoding algorithm to improve the error-correcting capability of some BCH codes by searching the relation tables is presented. It is found out that all the error patterns whose weights are equal to t + 1 and that BCH (n, k, t) codes can correct. Then these error patterns and those whose weights are less than t + 1 are ordered according to their corresponding syndrome values. The ordered error patterns are optimized to be stored in hardware devices so that decoding can be realized by searching the relation tables. The simulation results show that when the code bits and information bits are the same, this decoding method can correct more error bits than usual decoding methods. The decoding circuits are comparatively simpler and the decoding speeds are faster. This decoding method of improving the error-correcting capability is applicable to all binary linear cyclic codes.
出处 《东南大学学报(自然科学版)》 EI CAS CSCD 北大核心 2005年第3期328-332,共5页 Journal of Southeast University:Natural Science Edition
基金 国家高技术研究发展计划(863计划)资助项目(2003AA1Z1110) 江苏省高技术研究计划资助项目(BG2004002) 教育部科学技术研究重点资助项目(02171).
关键词 BCH码 错误图样 伴随式 陪集 循环码 Algorithms Codes (symbols) Error correction Hardware
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参考文献10

  • 1Joiner L L, Komo J J. Decoding binary BCH codes[ A ]. In: Proceedings of IEEE Southeastcon Conference[C]. Raleigh, 1995.67-73.
  • 2Lu E H, Chang T. New decoder for double-error-correcting binary BCH codes [ J ]. IEE Proceedings on Communications, 1996, 143(3) :129 - 132.
  • 3Hwang T. Parallel decoding of binary BCH codes [ J ].IEE Electronics Letters, 1991, 27(24) :2223 - 2225.
  • 4Chen Chin-Long. High-speed decoding of BCH codes[J]. IEEE Transactions on Information Theory, 1981,27 (2) :254 - 256.
  • 5孙怡,田上力,林建英.BCH码译码器的FPGA实现[J].电路与系统学报,2000,5(4):98-100. 被引量:5
  • 6王建华,郑坤,张军.基于VC的BCH码迭代译码算法实现[J].哈尔滨师范大学自然科学学报,2003,19(5):26-30. 被引量:2
  • 7张瑞华.BCH(31,21)码的解码及其软件实现[J].通信技术,2002,35(11X):22-24. 被引量:5
  • 8Vardy AI Be'ery Y. Maximum-likelihood soft decision decoding of BCH codes [ J ]. IEEE Transactions on Information Theory, 1994, 40(2) :546-554.
  • 9Koga K. A simple decoding of BCH codes over GF( 2m ) [ J ]. IEEE Transactions on Communications,1998, 46(6) : 709-716.
  • 10Sklar Bernard. Digital communications: fundamentals and applications. 2nd ed. [ M ]. New Jersey: Prentice Hall PTR, 2001. 349-356.

二级参考文献7

  • 1姚明余,忻鼎稼.BCH码的一种新的译码方法[J].通信学报,1989,10(5):10-14. 被引量:9
  • 2张呜瑞 等.编码理论[M].北京航空航天大学出版社,1990..
  • 3玉新梅.纠错码原理与方法[M].西安电子科技大学出版社,1991.12.
  • 4Massey, J L. Shift Register Synthesis and BCH Decoding[J].IEEE Trans. Information Theory, 1969,15:122-127
  • 5Berlekamp, E R. On Decoding Binary BCH Codes[J].IEEE Trans. Information Theory,1965,11:577-580
  • 6Stephen G Wilson. Digital Modulation and Coding[M]. Prentice-Hall, 1996
  • 7刘宝琴,张芳兰,田立生.ALTERA可编程逻辑器件及其应用[M].北京:清华大学出版社,1998年.

共引文献9

同被引文献28

  • 1EI-Medany W M 等.VHDL implementation of a BCH minimum weight decoder for double error[C].8th National Radio Science Conference,March 27-29,2001,Mansoura Univ.,Egypt.
  • 2Martin P A 等.Soft Input Soft Output List-based decoding algorithm[C].ISIT 2002,Lausanne,Switzerland,June 30-July 5,2002.
  • 3Guruswami V,Sudan M.Reflections on improved decoding of Reed Solomon and Algebraic-geometry codes.IEEE Trams.on Information Theory,Vol.45,No.6,Sep.1999.
  • 4赵晓群.现代编码理论.武汉:华中科技大学出版社,2007.
  • 5Wells R B. Applied Coding and Information Theory for Engineers. Englewood Cliffs, New Jersey: Prentice-Hall, 1999.
  • 6OKAMOTO E. Cryptesystems based on Polynomials over Finite Fields[C]. India:Prec the Information Theory Workshop 2002.
  • 7LIDL R, NIEDERREITER H. Introduction to Finite Fields andTheir Plicatious[M]. Cambridge: Cambridge University Press, 1994.
  • 8KITSOS P, THEODORIDIS G, KOUFOPAVLOU. An eficientreconfigurable multier architecture for GF(2) [J]. Microelectronics J, 2003, 34(10) : 975-980.
  • 9WU H. Bit-parallel Finite Field Multiplier and Squarerusing Polynomial Basis[J]. IEEE Trans Computers, 2002, 51(07): 750-758.
  • 10SONG L, PARHI K K. Eicient Finite Fields Serial / Parallel Multiplication[C]. Chicago:Proc Int Conf Application Specific System Architectures and Pl'ocessers. 1996:72-82.

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