摘要
测试台实现把接收到的±2. 5VPCM码流还原出原始数据信息,按照帧结构分路存储。该电路设计的关键是实现硬件同步,包括时钟同步、码同步和帧同步,并进行串并转换完成对高速PCM码的解调。给出了±2. 5VPCM码流经AD8138差分输出驱动后到HCPL2631光电耦合器的电路,将差分信号转换成TTL逻辑电平。本文主要详细讲述了如何利用差分变换后的波形提取位时钟信号。该电路设计已用于某弹上设备测试台,具有工作稳定,抗干扰能力强的特点。
Test platform accomplished the mission of decoding high-speed difference PCM signal received, and recording data by frame. Also it achieved serial-parallel data conversion. The key is how to implement hardware synchronization, concludes clock-synchronization, code-synchronization and frame-synchronization. The paper introduce the circuit on conversing difference signal to TTL , and introduce in detail how to gained bit-clock signal . The circuit has applied in one test platform of some type of missiles successfully. It has the merit of stabilization and anti-jamming.
出处
《航空计算技术》
2005年第1期79-81,共3页
Aeronautical Computing Technique
基金
国家自然科学基金资助项目(60104005)。
关键词
差分输出驱动
PCM码
AD8138
码同步
帧同步
解码
difference output driving
PCM
AD8138
code-synchronization
frame-synchronization
decoding
